Achieving Sub-Microsecond Jitter with EtherCAT Distributed Clocks

Deterministic communication is the foundation of synchronized multi-axis motion control. In this post, we break down the architecture decisions that allow the Adeeb EtherCAT Master to achieve sub-microsecond jitter on standard hardware.

The Problem

Standard Ethernet was never designed for real-time control. Packet scheduling, interrupt coalescing, and kernel preemption all introduce timing uncertainty that compounds across a distributed network of servo drives.

For coordinated motion — where 128 axes must hit their trajectory targets within the same 250μs window — jitter tolerance is measured in nanoseconds, not milliseconds.

Our Approach

Three architectural decisions make sub-microsecond jitter achievable:

1. PREEMPT_RT kernel with CPU isolation — Dedicated cores for the EtherCAT cyclic task, with all other interrupts migrated away.

2. Distributed clock synchronization — IEEE 1588-based DC sync propagates a reference clock to all slaves, compensating for cable propagation delay and drift.

3. Zero-copy PDO exchange — Process data is memory-mapped directly from the DMA ring buffer to application space, eliminating copy overhead.

Results

On a standard Intel i7 with PREEMPT_RT 6.1:

Metric	Value
Mean cycle time	1000.000 μs
Max jitter	0.847 μs
99.99th percentile	0.612 μs

These measurements were taken over 72 hours of continuous operation with 64 synchronized axes.

Key Takeaways

Sub-microsecond jitter doesn’t require specialized hardware or proprietary RTOS licenses. With careful kernel configuration, appropriate network architecture, and an EtherCAT stack designed for determinism, standard x86 platforms deliver the timing precision that multi-axis coordination demands.